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LTC2225 12-Bit, 10Msps Low Power 3V ADC
FEATURES

DESCRIPTIO
Sample Rate: 10Msps Single 3V Supply (2.7V to 3.4V) Low Power: 60mW 71.3dB SNR 90dB SFDR No missing codes Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm x 5mm) QFN Package
The LTC(R)2225 is a 12-bit 10Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2225 is perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. DC specs include 0.3LSB INL (typ), 0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation
TYPICAL APPLICATIO
REFH REFL FLEXIBLE REFERENCE
OVDD 12-BIT PIPELINED ADC CORE
INL ERROR (LSB)
+
ANALOG INPUT INPUT S/H
CORRECTION LOGIC
OUTPUT DRIVERS
-
D11 * * * D0 OGND
CLOCK/DUTY CYCLE CONTROL
2225 TA01
CLK
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Typical INL, 2V Range
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4096
2225 G01
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2225fa
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LTC2225
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SENSE MODE VCM D11 D10 VDD D9 OF
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... -0.3V to 1V Analog Input Voltage (Note 3) ..... -0.3V to (VDD + 0.3V) Digital Input Voltage .................... -0.3V to (VDD + 0.3V) Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2225C ............................................... 0C to 70C LTC2225I .............................................-40C to 85C Storage Temperature Range ..................-65C to 125C
32 31 30 29 28 27 26 25 AIN+ 1 AIN- 2 REFH 3 REFH 4 REFL 5 REFL 6 VDD 7 GND 8 9 10 11 12 13 14 15 16
SHDN OE D0 D1 NC CLK NC D2
24 D8 23 D7 22 D6 33 21 OVDD 20 OGND 19 D5 18 D4 17 D3
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN
TJMAX = 125C, JA = 34C/W EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC2225CUH LTC2225IUH
QFN PART MARKING 2225*
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
MIN 12 -1.1 -0.7 -12 -2.5
TYP
MAX
UNITS Bits
Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference SENSE = 1V

0.3 0.15 2 0.5 10 30 5 0.25
1.1 0.7 12 2.5
V/C ppm/C ppm/C LSBRMS
2225fa
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LSB LSB mV %FS
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LTC2225
A ALOG I PUT
SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS -AIN-) 2.7V < VDD < 3.4V (Note 7) Differential Input (Note 7) Single Ended Input (Note 7) 0V < AIN+, AIN- < VDD 0V < SENSE < 1V

Analog Input Range (AIN+
Analog Input Common Mode(AIN+ +AIN-)/2 Analog Input Leakage Current SENSE Input Leakage MODE Pin Leakage Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio
DY A IC ACCURACY
SYMBOL SNR SFDR SFDR S/(N+D) IMD PARAMETER Signal-to-Noise Ratio Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 5MHz Input 70MHz Input 5MHz Input 70MHz Input 5MHz Input 70MHz Input 5MHz Input 70MHz Input fIN1 = 4.3MHz, fIN2 = 4.6MHz

Signal-to-Noise Plus Distortion Ratio Intermodulation Distortion
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0
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WU
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MIN 1 0.5 -1 -3 -3
TYP 1.5 1.5
MAX 1.9 2 1 3 3
UNITS V V V A A A ns psRMS dB
0.5V to 1V
0 0.2 80
MIN 69.8 76 82 69.5
TYP 71.3 70.7 90 85 90 90 71.3 70.4 90
MAX
UNITS dB dB dB dB dB dB dB dB dB
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(Note 4)
MIN 1.475 TYP 1.500 25 3 4 MAX 1.525 UNITS V ppm/C mV/V
2.7V < VDD < 3.4V -1mA < IOUT < 1mA
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LTC2225 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA 1.79 0.09 V V High Level Output Voltage Low Level Output Voltage IO = -200A IO = 1.6mA 2.49 0.09 V V Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3V IO = -10A IO = -200A IO = 10A IO = 1.6mA

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V VIN = 0V to VDD (Note 7)

LOGIC INPUTS (CLK, OE, SHDN) 2 0.8 -10 3 10 V V A pF
LOGIC OUTPUTS 3 50 50 2.7 2.995 2.99 0.005 0.09 0.4 pF mA mA V V V V
POWER REQUIRE E TS
SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power Nap Mode Power
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 8)
CONDITIONS (Note 9) (Note 9)

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MIN
TYP
MAX
UNITS
MIN 2.7 0.5
TYP 3 3 20 60 2 15
MAX 3.4 3.6 23 69
UNITS V V mA mW mW mW
SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK
2225fa
LTC2225
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL fs tL PARAMETER Sampling Frequency CLK Low Time CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7)

TI I G CHARACTERISTICS
tH
tAP tD
Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential drive, unless otherwise noted.
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL, 2V Range
1.0 0.8 0.6
DNL ERROR (LSB) INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4096
2225 G01
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4096
2225 G02
AMPLITUDE (dB)
0.4
UW
UW
MIN 1 40 5 40 5
TYP 50 50 50 50 0
MAX 10 500 500 500 500
UNITS MHz ns ns ns ns ns
CLK High Time
Sample-and-Hold Aperture Delay CLK to DATA delay Data Access Time After OE BUS Relinquish Time

1.4
2.7 4.3 3.3 5
5.4 10 8.5
ns ns ns Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with differential drive. Note 9: Recommended operating conditions.
Typical DNL, 2V Range
1.0 0.8 0.6 0.4
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
8192 Point FFT, fIN = 5.1MHz, -1dB, 2V Range
0
1
3 2 FREQUENCY (MHz)
4
5
2225 G03
2225fa
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LTC2225 TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 70.1MHz, -1dB, 2V Range
0 -10 -20 -30
AMPLITUDE (dB)
0 -10 -20 -30 60000 50000
COUNT
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 1 3 2 FREQUENCY (MHz) 4 5
2225 G04
AMPLITUDE (dB)
SNR vs Input Frequency, -1dB, 2V Range
75 74 73 72 71 70 69 68 67 66 65 0 10 40 30 20 50 60 INPUT FREQUENCY (MHz) 70
SFDR (dBFS)
90 85 80 75 70 65 0 10 40 60 30 50 20 INPUT FREQUENCY (MHz) 70
SNR AND SFDR (dBFS)
SNR (dBFS)
SNR vs Input Level, fIN = 5MHz, 2V Range
80 dBFS 70 60 50 40 30 20 10 -0 -70 -60 -50 -40 -30 -20 INPUT LEVEL (dBFS) -10 0 dBc
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)
6
UW
2225 G07
8192 Point 2-Tone FFT, fIN = 4.3MHz and 4.6MHz, -1dB, 2V Range
70000
Grounded Input Histogram
61758
-40 -50 -60 -70 -80 -90 -100 -110 -120 0 0 1 3 2 FREQUENCY (MHz) 4 5
2225 G05
40000 30000 20000 10000 2155 2048 2049 CODE 1607 2050
2225 G06
SFDR vs Input Frequency, -1dB, 2V Range
100 95
90 100
SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, -1dB
80
70
60 0 2 10 12 4 6 8 SAMPLE RATE (Msps) 14
2225 G09
2225 G08
SFDR vs Input Level, fIN = 5MHz, 2V Range
120 110 100 90 80 70 60 50 40 30 20 10 0 -70 -60 -50 -40 -30 -20 INPUT LEVEL (dBFS) -10 0 90dBc SFDR REFERENCE LINE dBc dBFS
2225 G10
2225 G11
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LTC2225 TYPICAL PERFOR A CE CHARACTERISTICS
IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
25 1.0 0.9 2V RANGE 20 1V RANGE
IOVDD (mA) IVDD (mA)
15
10 0 2 10 4 6 8 SAMPLE RATE (Msps) 12 14
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1F ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2F ceramic chip capacitor and to ground with a 1F ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1F ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2F ceramic chip capacitor and to ground with a 1F ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. NC (Pins 12, 13): Do Not Connect These Pins. D0 - D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. VDD selects 2's complement output format and turns the clock duty cycle stabilizer off.
2225fa
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IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB, OVDD = 1.8V
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 8 6 4 10 SAMPLE RATE (Msps) 12 14
2225 G12
2225 G13
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LTC2225
PI FU CTIO S
SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a 0.5V input range. VDD selects the internal reference and a 1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of VSENSE. 1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2F ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.
FUNCTIONAL BLOCK DIAGRA
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE
AIN-
SECOND PIPELINED ADC STAGE
VCM 2.2F
1.5V REFERENCE
RANGE SELECT
REFH SENSE REF BUF
DIFF REF AMP
REFH
1F
Figure 1. Functional Block Diagram
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THIRD PIPELINED ADC STAGE
FOURTH PIPELINED ADC STAGE
FIFTH PIPELINED ADC STAGE
SIXTH PIPELINED ADC STAGE
SHIFT REGISTER AND CORRECTION
REFL
INTERNAL CLOCK SIGNALS
OVDD OF D11
CLOCK/DUTY CYCLE CONTROL
CONTROL LOGIC
OUTPUT DRIVERS
* * * D0
0.1F
REFL CLK MODE SHDN OE
2225 F01
OGND
2.2F 1F
2225fa
LTC2225 TI I G DIAGRA
ANALOG INPUT
CLK tD D0-D11, OF N-5 N-4 N-3 N-2 N-1 N
2225 TD01
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log ((V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.
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tAP N tH tL N+1 N+2 N+3 N+4 N+5
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Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.
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LTC2225
APPLICATIO S I FOR ATIO
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2225 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2225 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high,
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the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2225 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.
LTC2225 VDD 15 AIN+ VDD 15 CPARASITIC 1pF VDD CLK CPARASITIC 1pF CSAMPLE 4pF CSAMPLE 4pF AIN-
2225 F02
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Figure 2. Equivalent Input Circuit
During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling
2225fa
LTC2225
APPLICATIO S I FOR ATIO
capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN- should be connected to VCM or a low noise reference voltage between 0.5V and 1.5V. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing 0.5V for the 2V range or 0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2F or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2225 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.
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For the best performance, it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2225 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100 for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.
VCM 2.2F 0.1F ANALOG INPUT T1 1:1 25 25 T1 = MA/COM ETC1-1T 25 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 25 0.1F 12pF AIN-
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AIN+
LTC2225
Figure 3. Single-Ended to Differential Conversion Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25 resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the
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LTC2225
APPLICATIO S I FOR ATIO
sample-and-hold charging glitches and limiting the wideband noise at the converter input.
1.5V
VCM HIGH SPEED DIFFERENTIAL 25 AMPLIFIER ANALOG INPUT 2.2F AIN+ LTC2225
+
CM
+
12pF
-
-
25
AIN-
2225 F04
Figure 4. Differential Drive with an Amplifier
2.2F
VCM 1k 0.1F ANALOG INPUT
1k
2.2F
25
AIN
+
LTC2225
12pF
25
0.1F
AIN-
2225 F05
Figure 5. Single-Ended Drive
12k
Reference Operation Figure 6 shows the LTC2225 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (1V differential) or 1V (0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.
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LTC2225 VCM 2.2F 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V 4 1.5V BANDGAP REFERENCE TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 * VSENSE FOR 0.5V < VSENSE < 1V 1F 0.1F DIFF AMP 1F REFL INTERNAL ADC LOW REFERENCE
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Figure 6. Equivalent Reference Circuit
1.5V
VCM 2.2F
0.75V 12k
SENSE 1F
LTC2225
2225 F07
Figure 7. 1.5V Range ADC
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by applying its output directly or through a resistor divider to SENSE.
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LTC2225
APPLICATIO S I FOR ATIO
It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor. Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A differential clock can also be used along with a low-jitter CMOS converter before the CLK pin (see Figure 8). The noise performance of the LTC2225 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2225 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation.
4.7F FERRITE BEAD 0.1F CLEAN SUPPLY
CLK 100
LTC2225
2225 F08
IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
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An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2225 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2225 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V Range) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V -0.000488V -0.000976V -0.999512V -1.000000V <-1.000000V OF 1 0 0 0 0 0 0 0 0 1 D11 - D0 (Offset Binary) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11 - D0 (2's Complement) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
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LTC2225
APPLICATIO S I FOR ATIO
Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2225 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format Using the MODE pin, the LTC2225 parallel digital output can be selected for offset binary or 2's complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2's complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.
LTC2225 OVDD VDD VDD 0.5V TO 3.6V 0.1F OVDD DATA FROM LATCH OE OGND PREDRIVER LOGIC 43 TYPICAL DATA OUTPUT
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Figure 9. Digital Output Buffer
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Table 2. MODE Pin Function
MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Offset Binary Offset Binary 2's Complement 2's Complement Clock Duty Cycle Stablizer Off On On Off
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Overflow Bit When OF outputs a logic high the converter is either overranged or underranged. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The output Hi-Z state can be used to multiplex the data bus of several LTC2225s. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep
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LTC2225
APPLICATIO S I FOR ATIO
and nap modes, all digital outputs are disabled and enter the Hi-Z state. Grounding and Bypassing The LTC2225 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1F capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2F
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capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2225 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2225 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.
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LTC2225
C3 0.1F VCM C4 0.1F 1 OE1 VCC RN1D 33 RN1C 33 RN1B 33 RN1A 33 RN2D 33 RN2C 33 RN2B 33 RN2A 33 RN3D 33 RN3C 33 RN3B 33 RN3A 33 RN4D 33 RN4C 33 RN4B 33 RN4A 33 C17 0.1F VCC R11 10k 8 7 NC7SV86P5X 2 4 6 8 C20 0.1F C26 10F 6.3V VCC LT1763 R17 105k R18 100k VDD VDD E3 GND C27 0.01F C28 1F E2 VDD 3V 6 C18 0.1F 5 R12 10k R13 10k 7 1 2 3 REFH D0 15 16 17 18 19 22 23 24 25 26 27 28 21 20 VCC C16 0.1F D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 32 VDD VCM OF OVDD OGND GND 33 SENSE MODE D11 C14 0.1F VCM 31 C15 2.2F 30 29 REFH REFL REFL VDD GND CLK SHDN OE C7 2.2F C8 0.1F 5 6 C9 1F VDD C11 0.1F 8 9 10 VDD VDD 11 GND JP2 OE GND VDD JP1 SHDN VDD 7 4 AIN- NC 14 AIN+ NC 13 LTC2225 12 R6 24.9 24 OE2 GND 4 LE1 GND
R5 50 48 10
3201S-40G1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
L1 BEAD
C5 4.7F 6.3V C6 1F
R7 1k
C10 0.1F
J3 CLOCK INPUT
C12 0.1F
NC7SVU04
R8 49.9 C13 0.1F VDD
R9 1k
47 I0 46 I1 44 I2 43 I3 41 I4 40 I5 38 I6 37 I7 36 I8 35 I9 33 I10 32 I11 30 I12 29 I13 27 I14 26 I15 2 O0 3 O1 5 O2 6 O3 8 O4 9 O5 11 O6 12 O7 13 O8 14 O9 16 O10 17 O11 19 O12 20 O13 22 O14 23 O15
NC7SVU04 R10 33
JP3 SENSE JP4 MODE VDD 1 R14 1k 3 5 7 GND 1/3VDD 2/3VDD R15 1k C19 0.1F R16 1k VDD
39 39 37 37 35 35 33 33 31 31 29 29 27 27 25 25 23 23 21 21 19 19 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1
VDD
1
VDD
2
VCM
3
VCM
4
24LC025 1 VCC A0 2 WP A1 3 A2 SCL 4 A3 SDA 1 8 IN OUT 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN
E1 EXT REF
EXT REF 5 6
VCC
C21 0.1F
C22 0.1F
C23 0.1F
C24 0.1F
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C25 4.7F E4 PWR GND
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APPLICATIO S I FOR ATIO
VDD
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VCC VCC R2 24.9 74VCX16373MTD 34 45 39 42 25 LE2 VCC 18 VCC GND 15 GND GND 21 GND VCC 31 C2 12pF GND GND 28 R3 24.9 R4 24.9 T1 ETC1-1T 5 1 2 4
J1 ANALOG INPUT
R1 OPT
C1 0.1F
*
*3
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APPLICATIO S I FOR ATIO
Silkscreen Top
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Topside Inner Layer 2 GND
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LTC2225
APPLICATIO S I FOR ATIO
Inner Layer 3 Power
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Bottomside Silkscreen Bottom
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LTC2225
PACKAGE DESCRIPTIO U
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 3.45 0.10 (4-SIDES)
(UH32) QFN 1004
5.50 0.05 4.10 0.05 3.45 0.05 (4 SIDES)
0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC2225
RELATED PARTS
PART NUMBER LTC1748 LTC1750 LT1993-2 LT1994 LTC2202 LTC2208 LTC2220-1 LTC2224 LTC2225 LTC2226 LTC2227 LTC2228 LTC2229 LTC2236 LTC2237 LTC2238 LTC2239 LTC2245 LTC2246 LTC2247 LTC2248 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2284 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps, 5V ADC 14-Bit, 80Msps, 5V Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 12-Bit, 10Msps, 3V ADC, Lowest Power 12-Bit, 25Msps, 3V ADC, Lowest Power 12-Bit, 40Msps, 3V ADC, Lowest Power 12-Bit, 65Msps, 3V ADC, Lowest Power 12-Bit, 80Msps, 3V ADC, Lowest Power 10-Bit, 25Msps, 3V ADC, Lowest Power 10-Bit, 40Msps, 3V ADC, Lowest Power 10-Bit, 65Msps, 3V ADC, Lowest Power 10-Bit, 80Msps, 3V ADC, Lowest Power 14-Bit, 10Msps, 3V ADC, Lowest Power 14-Bit, 25Msps, 3V ADC, Lowest Power 14-Bit, 40Msps, 3V ADC, Lowest Power 14-Bit, 65Msps, 3V ADC, Lowest Power 14-Bit, 80Msps, 3V ADC, Lowest Power 10-Bit, 105Msps, 3V ADC, Lowest Power 10-Bit, 125Msps, 3V ADC, Lowest Power 12-Bit, 105Msps, 3V ADC, Lowest Power 12-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, 105Msps, 3V ADC, Lowest Power 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN 75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN 120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN 205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN 211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN 205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0106 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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